Megawin MCU crack MPC89 and MPC82 chip break
Megawin Technology was formed by a group of IC design and sale specialists in 1999.Since March 31, 2012, Megawin has applied 134 patents, of which 60 have been certified, growing rapidly in MCU industry. The production of 8051 MCU is favoured with strong anti-interference ability and low price. STC's STC89 and STC12 series are produced by Megawin, pasted and sold by Shenzhen Hongjing. The Megawin's MPC89E series microcontrollers can be completely compatible instead of STC89 Series MCU, MPC82 series of microcontrollers can be fully compatible instead of STC12 Series MCU, which means you can replace the STC MCU.We offer the full range of Megawin MCU crack service.
Wednesday, August 29, 2012
MPC89E54 Crack
Megawin MCU crack MPC89 and MPC82 chip break
Megawin Technology was formed by a group of IC design and sale specialists in 1999.Since March 31, 2012, Megawin has applied 134 patents, of which 60 have been certified, growing rapidly in MCU industry. The production of 8051 MCU is favoured with strong anti-interference ability and low price. STC's STC89 and STC12 series are produced by Megawin, pasted and sold by Shenzhen Hongjing. The Megawin's MPC89E series microcontrollers can be completely compatible instead of STC89 Series MCU, MPC82 series of microcontrollers can be fully compatible instead of STC12 Series MCU, which means you can replace the STC MCU.We offer the full range of Megawin MCU crack service.
MPCseries
MPC89E51 MPC89E52 MPC89E53 MPC89E54 MPC89E58 MPC89E515
MPC89LE51 MPC89LE52 MPC89LE53 MPC89LE54 MPC89LE58 MPC89LE515
MPC82E52 MPC82E54 MPC82LE52 MPC82LE54
Wednesday, August 15, 2012
TMS320 Logical DMA Channels & DMA Handles
TMS320 Logical DMA Channels & DMA Handles
The logical DMA channel is the fundamental software abstraction for characterizing hardware DMA resources and services. Each logical DMA channel represents a private hardware DMA resource and a private state identified by and accessed through a DMA handle. Applications are in charge of the physical DMA resources and grant IDMA3 channel handles to algorithms that request them using the IDMA3 interface.
TMS320 ACPY3_Params Structure Fields
TMS320 ACPY3_Params Structure Fields
transferType Transfer type: ACPY3_1D1D, ACPY3_1D2D, ACPY3_2D1D or ACPY3_2D2D
srcAddr Source Address of the DMA transfer.
dstAddr Destination Address of the DMA transfer.
elementSize Number of consecutive bytes in each 1D transfer vector (ACNT).
numElements Number of 1D vectors in 2D transfers (BCNT).
numFrames Number of 2D frames in 3D transfers (CCNT).
srcElementIndex Offset in number of bytes from beginning of each 1D vector to the beginning of the
next 1D vector (SBIDX).
dstElementIndex Offset in number of bytes from beginning of each 1D vector to the beginning of the
next 1D vector (DBIDX).
srcFrameIndex Offset in number of bytes from beginning of the first 1D vector of source frame to
the beginning of the first element in the next frame. (SCIDX: signed value between -32768 and 32767)
dstFrameIndex Offset in number of bytes from beginning 1D vector of first element in destination frame to the beginning of the first element in next frame. (DCIDX: signed value between -32768 and 32767).
waitId For a linked transfer entry:
-1 : no individual wait on this transfer 0 <= waitId < numWaits : this transfer can be waited on or polled for completion. Ignored for single-transfers and for the last transfer in a sequence of linked transfers, which are always synchronized with waitId == (numWaits – 1).
transferType Transfer type: ACPY3_1D1D, ACPY3_1D2D, ACPY3_2D1D or ACPY3_2D2D
srcAddr Source Address of the DMA transfer.
dstAddr Destination Address of the DMA transfer.
elementSize Number of consecutive bytes in each 1D transfer vector (ACNT).
numElements Number of 1D vectors in 2D transfers (BCNT).
numFrames Number of 2D frames in 3D transfers (CCNT).
srcElementIndex Offset in number of bytes from beginning of each 1D vector to the beginning of the
next 1D vector (SBIDX).
dstElementIndex Offset in number of bytes from beginning of each 1D vector to the beginning of the
next 1D vector (DBIDX).
srcFrameIndex Offset in number of bytes from beginning of the first 1D vector of source frame to
the beginning of the first element in the next frame. (SCIDX: signed value between -32768 and 32767)
dstFrameIndex Offset in number of bytes from beginning 1D vector of first element in destination frame to the beginning of the first element in next frame. (DCIDX: signed value between -32768 and 32767).
waitId For a linked transfer entry:
-1 : no individual wait on this transfer 0 <= waitId < numWaits : this transfer can be waited on or polled for completion. Ignored for single-transfers and for the last transfer in a sequence of linked transfers, which are always synchronized with waitId == (numWaits – 1).
TMS320 ACPY3 Functions
TMS320 ACPY3 Functions
ACPY3_activate() Activates given channel. Take over shared resources prior to use.
ACPY3_deactivate() Deactivates given channel. Give back shared resources at the end of use.
ACPY3_complete() Check if the data transfers on a specific logical channel have completed.
ACPY3_completeLinked() Check if an individual transfer on a specific logical channel have completed.
ACPY3_configure() Configure a logical channel.
ACPY3_exit() Free resources used by the ACPY3 module [FRAMEWORK API]
ACPY3_setFinal() Dynamically change the number of transfers in a sequence of linked transfers. Sets given transferNo as the last in a sequence of linked transfers.
ACPY3_init() Initialize the ACPY3 module. [FRAMEWORK API]
ACPY3_fastConfigure16b() Modify a single (16-bit) parameter of the logical DMA Channel.
ACPY3_fastConfigure32b() Modify a single (32-bit) parameter of the logical DMA Channel.
ACPY3_start() Issue a request for a data transfer using current channel settings.
ACPY3_wait() Wait for all data transfers to complete on a specific logical channel.
ACPY3_waitLinked() Wait for an individual data transfer to complete on the logical channel.
ACPY3_activate() Activates given channel. Take over shared resources prior to use.
ACPY3_deactivate() Deactivates given channel. Give back shared resources at the end of use.
ACPY3_complete() Check if the data transfers on a specific logical channel have completed.
ACPY3_completeLinked() Check if an individual transfer on a specific logical channel have completed.
ACPY3_configure() Configure a logical channel.
ACPY3_exit() Free resources used by the ACPY3 module [FRAMEWORK API]
ACPY3_setFinal() Dynamically change the number of transfers in a sequence of linked transfers. Sets given transferNo as the last in a sequence of linked transfers.
ACPY3_init() Initialize the ACPY3 module. [FRAMEWORK API]
ACPY3_fastConfigure16b() Modify a single (16-bit) parameter of the logical DMA Channel.
ACPY3_fastConfigure32b() Modify a single (32-bit) parameter of the logical DMA Channel.
ACPY3_start() Issue a request for a data transfer using current channel settings.
ACPY3_wait() Wait for all data transfers to complete on a specific logical channel.
ACPY3_waitLinked() Wait for an individual data transfer to complete on the logical channel.
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